Faster Incremental VLSI Placement Optimization
نویسندگان
چکیده
A new incremental approach to placement optimization is proposed in this paper. The approach is based on the sequence pair representation and employs incremental constraint graph computation and incremental longest paths computation. Upper and lower bounds on the average computational complexity are derived and new algorithms are proposed. The average computational complexity of the implemented algorithms is close to , where is the number of modules in the placement problem, for a single placement update iteration. This is a significant improvement over known “brute force” algorithms. Two major advantages of an incremental approach are: 1) a road is paved to efficient incremental routing, and 2) it is (near) optimal in terms of information efficiency. This faster and accurate placement tool will be able to tackle substantially larger VLSI layout designs. Experimental results clearly demonstrate the effectiveness of the approach.
منابع مشابه
Discrete Multi Objective Particle Swarm Optimization Algorithm for FPGA Placement (RESEARCH NOTE)
Placement process is one of the vital stages in physical design. In this stage, modules and elements of circuit are placed in distinct locations according to optimization basis. So that, each placement process tries to influence on one or more optimization factor. In the other hand, it can be told unequivocally that FPGA is one of the most important and applicable devices in our electronic worl...
متن کاملOptimization of Placement for Modern VLSI Design
The VLSI placement problem is to place objects into a fixed die such that there are no overlaps among objects and some cost metrics (wire length, routability) are optimized. The nature of multiple objects and incremental design process for modern VLSI design demands Advanced Incremental Placement Techniques. Incremental placement changes either the wire length or the Placement Density of an exi...
متن کاملTCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans
We extend in this paper the concept of the P-admissible floorplan representation to that of the P*-admissible one. A P*-admissible representation can model the most general floorplans. Each of the currently existing P*-admissible representations, SP, BSG, and TCG, has its strengths as well as weaknesses. We show the equivalence of the two most promising P*-admissible representations, TCG and SP...
متن کاملA Fast Neural{Network Algorithm for Cell Placement
|Cell placement is an important phase of current VLSI circuit design styles as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) have been successful in solving this problem, they are known to be slow. In this paper, we propose a neural network algorithm that produces solutions as good as SA in substantiall...
متن کامل